In the development of integrated circuit (IC) manufacturing technology, photolithography has always been a major technology of semiconductor patterning. Various patterns on a reticle may be sequentially imaged onto a photoresist layer on a wafer by a photolithography system with a precise alignment. After developing, desired patterns may be formed on the wafer. Because an IC may include a plurality of layers of circuit structures stacking together, an alignment accuracy of every circuit layer and adjacent circuit layers may need to be ensured. If the alignment accuracy is beyond a predetermined range, it may cause the entire IC to be unable to achieve the design target.
Overlay is a parameter used to evaluate an alignment status of patterns formed by a current process layer and patterns formed by a previous process layer. In an IC manufacturing process, the alignment accuracy of a current process layer and the alignment accuracy of a previous process layer may be measured. If a positioning error exists between an exposure layer of the current process layer and an exposure layer of the previous process layer, an overlay error may be formed. In order to monitor and calibrate an alignment status of patterns formed by the previous process layer and patterns formed by the current process layer, overlay marks may often by formed with device patterns simultaneously; and the overlay error may be obtained by measuring the overlay marks formed by different process layers.
The overlay marks may be formed in scribe lines of different process layers. Specifically, a process for forming the overlay marks may include sequentially forming an outer overlay mark at a first position on a first process layer; forming an inner overlay mark at a same position (the first position) on a second process layer to align with the outer overlay mark on the first process layer; and forming another outer overlay mark at a second position on the second process layer used to align with another inner overlay mark on a subsequent third process layer.
In a photolithography system, a source asymmetry may be caused by an unaligned laser, usage life span of a pupil and/or diffracting optical electronic (DOE) devices, etc. The source asymmetry may be a major reason causing an overlay shift of a photolithography process. In order to ensure an alignment accuracy of the photolithography system, and reduce overlay errors, the source asymmetry may need to be monitored.
However, the existing technology for monitoring the source symmetry (or asymmetry) may be based on scanning and imaging the source by charge-coupled-detector (CCD) sensors. Such monitoring technology is a complex off-line monitoring process; and may affect a normal manufacturing process. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.